This site may earn chapter commissions from the links on this page. Terms of use.

TSMC-Fab

ARM and TSMC have had a joint agreement in place for several years to interact on R&D work and early validation on process nodes, and they've appear a major milestone in that process. Equally of yesterday, ARM is announcing that it has successfully validated a new 10nm FinFET design at TSMC.

The unnamed multi-core test chip features a quad-cadre CPU from ARM, codenamed Artemis, a single-core GPU as a proof of concept, and the chip'south interconnect and other various features.

Artemis-TestChip

This isn't an SoC that ARM will e'er bring to market place. Instead, it's purpose is to part as a validation tool and early reference design that helps both TSMC and ARM understand the specifics of the 10nm FinFET process as it moves towards commercial viability. I of the features that pure-play foundries like TSMC offering their customers are tools and libraries specifically designed to match the capabilities of each process node. Since each new node has its ain design rules and all-time practices, TSMC has to melody its offerings accordingly — and working with ARM to create a reasonably complex test bit is a win/win situation for both companies. ARM gets early insight into how best to tune upcoming Cortex processors; TSMC gets a standard compages and SoC design that closely corresponds to the bodily chips it'll be building for its customers as the new process node moves into production.

ARM-10nm-vs-16nm

The slide higher up shows the gains TSMC expects to realize from moving to 10nm as opposed to its current 16nm procedure. To the best of our knowledge, TSMC's 10nm is a hybrid process, but it's non articulate exactly what that hybrid looks like. Our current understanding is that the upcoming 10nm node would combine a 10nm FEOL (Front end end-of-line) with a 14nm BEOL (Back-end-of-line, which governs die size). EETimes, however, reported in March that TSMC'due south 10nm shrink would retain a 20nm minimum feature size, while its 7nm would deliver a 14nm minimum characteristic size (ten/20 and 7/14, respectively). Either style, Intel is the only visitor that has announced a "truthful" 14nm or 10nm die shrink. (The degree to which this procedure advantage materially helps Intel these days is open up to debate).

Ii things to note: Beginning, the tiptop line of the slide is potentially confusing. The 0.7x reduction of ability would be easier to read if ARM had labeled it "ISO Performance at 0.7x ability." Second, the performance gains predicted here purely as a outcome of the node transition are downright bloodless. I don't desire to read too much into these graphs considering information technology'south very early on days for 10nm, but there'south been a lot of talk around xvi/14nm as a long-lived node, and results like this are part of why — only a handful of companies will want to pay the extra costs for the additional masks required as part of the die shrink. TSMC has already said that information technology believes 10nm will be a relatively short-lived node, and that it thinks information technology'll accept more meaning customer appointment for 7nm.

None of this means that ARM can't deliver compelling improvements at 10nm — only the limited amount of lithography improvements hateful a heavier lift for the CPU research teams and design staff, who demand to notice additional tricks they tin apply to squeeze more performance out of silicon without driving up power consumption.

As for when 10nm might transport, past timelines suggest it'll be a while yet. TSMC has said it expects early 10nm tapeouts to bulldoze sizeable need starting in Q2 2022. While that's a quick turn-around for a company whose 16nm only entered book product in August 2022, the speed could be explained if the 10nm node continues to leverage TSMC's existing 20nm technology. Bear in mind that there'southward a pregnant delay between when TSMC typically ships hardware and when consumer products launch, particularly in mobile devices where multiple companies perform complex verification procedures on multiple parts of the chip.

Either way, this tapeout is a significant step forward for both ARM and TSMC, and 10nm will deliver improvements over the 16nm tech available today.